`timescale 1ns/1ns

module TestTop (
    input clk_50M,
    input [3:0] button_in,
    //output reg [3:0] LED,          //0->3代表板子上的LED0->LED3
    output wire [7:0] display_Pins,
    output wire [3:0] LED_Pins,
    output wire [5:0] contral_Pins
    
);

    wire [3:0] button_out;
    wire [3:0] button_long;
    wire [3:0] button_posedge;
    // wire button_mode;
    wire clk_1k;
    wire clk_1_posedge;
    wire [23:0] time_byte;
    wire [5:0] dp;

    div u_div(
    	.clk_50M       (clk_50M       ),
        .clk_1k        (clk_1k        ),
        .clk_1_posedge (clk_1_posedge )
    );
    
    
    button u_button(
        .clk            (clk_50M     ),
        // .clk_1k         (clk_1k      ),
        .rst_n          (button_in[3]        ),
        .button_in      (button_in   ),
        .button_posedge (button_posedge),
        .button_out     (button_out  ),
        .button_long    (button_long )
    );

    display u_display(
    	.clk          (clk_1k       ),
        .time_byte    (time_byte    ),
        .dp_in        (~dp        ),
        .display_Pins (display_Pins ),
        .contral_Pins (contral_Pins )
    );
    Timer u_Timer(
    	.clk            (clk_50M        ),
        .clk_1_posedge  (clk_1_posedge  ),
        .rst_n          (button_in[3]          ),
        .button_long    (button_long    ),
        .button_posedge (button_posedge ),
        .time_Byte      (time_byte      ),
        .LED_out        (LED_Pins       ),
        .dp_out         (dp             )
    );
    
endmodule